KiwiSDR: Wide-band SDR + GPS cape for the BeagleBone Black

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The KiwiSDR Kickstarter has launched.
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Very pleased to announce our partnership with Valent F(x), makers of the well-knownLOGI-Bone FPGA development board for the BeagleBone. They have essential manufacturing and Kickstarter experience.

6-March-2016

Lots going on. Business, manufacturing and shipping partners have all been engaged. Ten more prototypes are being fabricated which should be the same final design as the Kickstarter (KS) rewards. These ten will be distributed as more beta test sites. Hopefully KS backers will get a chance to try an online KiwiSDR before deciding to back. The KS campaign is almost finished. The KS financial analysis needed to validate reward prices is done. Now just a lot of pondering before pulling the switch..

7-February-2016

Our second Beta test KiwiSDR is now at the SK3W contest station, Fernebo, Sweden, courtesy of Gunnar Widell, SM3SGP. This KiwiSDR is also part of the SDR.hu network.

27-January-2016

Very pleased to report our first Beta test KiwiSDR installation at the Dept. of Electrical and Computer Engineering, University of Victoria, B.C., Canada, courtesy of Michael Cavallin, VE7XMC. Also, check out their QS1R-based WebSDR. This KiwiSDR is also part of the SDR.hu network.

16-January-2016

Our prototype SDRs are now part of the SDR.hu network courtesy of Andras Retzler, HA7ILM, developer of the OpenWebRX project.

The latest source code, Verilog and KiCAD PCB files have been updated on Github.

12-January-2016

The project name has been changed to “KiwiSDR” in recognition of the time we spend in New Zealand. There were obvious trademark problems with the previous name (WRX, “web receiver”), although I must say I was the happy owner of two Subarus during my time living in the snows of Colorado ski country. The “Kiwi with headphones” logo is courtesy of Hayes Roberts at bluebison.net. Thanks Hayes!

The performance problems mentioned below have been largely solved. So at this point I don’t see any potential problems that would prevent this project from being manufactured and sold. Very soon there is going to be a decision point of how to proceed. Kickstart? Self-funded organic growth? Partner with another company? Kickstarter is very interesting, not only from a fund raising aspect but because it can provide a good gauge of the market interest. I really don’t know how many people might want to buy this device. If I self-fund I need to build a reasonable quantity to lower manufacturing costs but then I run the risk of having unsold items if I miscalculate demand.

In some sense the fun part of this project is over and now the real work begins.

9-December-2015
Prototype PCBs Working

The prototype boards seem to work fine. There were a few components installed in the wrong places by the assembly house. This was partly my fault because of an ambiguous parts placement silkscreen.

After some effort the Verilog worked on the Artix 7 FPGA which is new on this board compared to the Spartan 6 used on the hand-wired prototype. With this larger FPGA a full four SDR channels, with independent waterfall DDCs, and 12 GPS receiver channels fit, with a fair amount of logic and DSP blocks left over. All but a few BRAMs (memory blocks) are used however.

A new scheme for speeding up the waterfall at higher zoom levels has been implemented. It essentially involves calculating the FFT on overlapping samples when the samples are being generated by the waterfall DDC at a rate slower than the desired display rate.

The highly-accurate timing from GPS location fixes now compensates the SDR frequency to cancel the temperature drift of the main 66.6 MHz oscillator. Since the Soft-GPS was going to be on the board anyway it made some sense to use an inexpensive XO (instead of a TCXO) to help keep the BOM cost low and let the GPS do the calibration and temperature compensation. Although an XO with relatively good phase noise performance had to be chosen to keep the ADC happy.

The big problem now is getting acceptable performance with all four SDR channels running simultaneously along with the GPS (since the waterfall DCC is tunable independently from the audio DDC it’s really an 8 channel SDR). I’ve made a lot of optimizations but the waterfall update rate is still too slow when more than two channels are in use. Fortunately between the FPGA logic, embedded FPGA CPU, Beagle and Javascript on the users’ browser there are plenty of different ways of distributing the tasks, buffering and latency. I’m having fun figuring out how to measure where the bottlenecks are and designing better solutions.


View of entire 0-30 MHz range:

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